![]() IF M 10 = 0 AND M 1 = 2 AND D 10 = 2 AND D 1 = 8 (representing the month February) OR IF M 1 = 4 OR 6 OR 9 OR 11 (M 1 = 1 & M 10 = 1) AND D 10 = 3 AND D 1 = 0 (representing months with thirty days in a month) Similarly, D 10 represents tens of days while D 1 represents units of days. M 10 represents Tens of months while M 1 represents Units of a month. The following logic was used in checking the state of the circuit with the Gregorian format and reacting appropriately. This module consisted of four seven segment displays where a pair represents either a month or date. The circuit used similar BCD and divide-by-twelve counters with a little more extra logic to match the Gregorian calendar format. The date module was the hardest of all the designs, as the circuit needed to match with the Gregorian format. Note that the clock is 24 hour clock and therefore goes from 00 to 23 for the hour hand.Īfter completion of the counter and the 24 hour time modules the last module to be designed was the Gregorian calendar circuit giving the date and month. The figure below shows the hour, minute, and seconds hands in HH:MM:SS format. For the hour hand, extra logic had to be added to comply with the 24 hour format. Circuit below shows how a pair of 74 chips was used to design a divide-by-sixty counter.Ī pair of the above circuit was used to generate the minute and the hour hand. The circuit also made use of six BCD (7448) and six seven segment displays, including two OR and one AND gates. The divide-by-twelve counters were used to provide the clock with the mod six operations. The 24 hour clock was designed using three pairs of Four bit BCD counters (7490) and Four bit divide-by-twelve counters (7492). The figure below is a logic diagram of 7490 as found in TTL datasheets.īelow is the LogicWorks figure of the counter/stop watch. For this design R0 inputs were used as reset inputs while R9 inputs were grounded. The 7490 chip counts only when exactly two inputs are low while the other two can assume any values. Table below indicates the behavior of the Four bit BCD decimal counter. The design of the counter included five 7490 chips, five 7448 BCD converters, five seven segment displays, two switches (one to clear/reset the counter, and another to stop/continue the stop clock), and one AND gate. The counter was designed using Four bit BCD decimal counter (7490 TTL chip). The counter / stop clock / stopwatch was the simplest module of the Digital clock. ![]() The figure below shows the top-down approach used to modularize the design. The Digital Clock had three parts to it: Clock having Hour hand, Minute hand, and Second hand Date having month and day counter having seconds and seconds/100. Modular approach to solving the Digital clock designĪ modular approach was used to break the design in a top-down fashion.
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